1. Field of the Invention
The present invention relates to a multiple output current mirror. Such current mirrors are commonly used in monolithic integrated circuits, for example as an active load, a current source, or a current polarity inverter.
2. Discussion of the Related Art
A current mirror reproduces an input current on at least one output. In this purpose, a current mirror uses bipolar transistors, for example PNP, having a common emitter and whose bases are connected to each other and to the collector of the transistor providing the input current. One basically considers that the emitter-base voltages Vbe of identical transistors formed on the same chip are identical. Two transistors having the same emitter surface will have substantially identical saturation currents. Thus, since the transistors are connected with a common emitter and have interconnected bases, the collector currents will also be identical.
A current mirror can be characterized by various operating parameters:
the mirror ratio which corresponds to the ratio between the reproduced current on one output and the input current; PA1 the output impedance; PA1 the frequency stability; PA1 the sensitivity to the gain variations of the constituting transistors; and PA1 the current operating range for a constant mirror ratio. PA1 the output matching ratio which corresponds to the ratio between the currents reproduced on two outputs of the mirror; and PA1 the effect of the number of outputs on the mirror ratio.
For a multiple output current mirror, two additional parameters are to be taken into account, that is:
FIG. 1 shows a basic current mirror having two out-puts and comprising three PNP transistors T1, T2, T3 having a common emitter. The emitters of the three transistors are connected to a supply voltage Vcc. The bases of the transistors are connected to a node A connected to the collector of transistor T1. The input current Iin to be reproduced on the mirror outputs originates from node A, that is from the collector of transistor T1, and the outputs correspond to the collector currents of transistors T1 and T2.
For a given input current Iin, the collector current of transistor T1 is equal to current Iin less the three base currents of transistors T1, T2 and T3. Assuming that the three transistors have the same emitter surface, this means that their respective base currents Ib are identical. So, the collector current Ic1 of transistor T1 is Ic1=Iin-3Ib. The emitter current Ie1 of transistor T1 is Ie1=Iin-2Ib. As transistors T1, T2, T3 have the same base-emitter voltage Vbe, they have the same emiter current. Therefore, the emitter currents Ie2 and Ie3 of transistors T2, T3 are also equal to Iin-2Ib. The collector currents Io1 and Io2 of transistors T2 and T3 are accordingly equal to Iin-3Ib.
The mirror ratio of such a current mirror is accordingly identical for each output. This mirror ratio is equal to 1-3/.beta., where .beta. is the current gain of the transistors, that is Ic/Ib. As this ratio is generally considered in first approximation as equal to 1, it can be considered that the real mirror ratio presents an "error" that is equal to 3/.beta.. In an example where .beta.=50, as usual for PNP transistors, this "error" is equal to 6% and the mirror ratio is equal to 0.94.
Such a circuit presents a low output impedance which causes current variations on the outputs when the output voltage varies due to the Early effect. Additionally, as the mirror ratio takes into account the number of base currents Ib on the node A, when the transistor number increases, this ratio decreases. Furthermore, as the gain of a transistor varies with the operating temperature, such a circuit can operate only on a small current range.
FIG. 2 shows a current mirror using a cascode configuration for limiting the Early effect and providing a very high output impedance. This circuit also improves the mirror ratio. Each mirror transistor T1, T2 and T3 is associated with a cascode PNP transistor. A first cascode transistor T4 has its emitter connected to the node A while its collector constitutes a second node B. Node B receives the base currents Ib of transistor T4 and of two other PNP transistors T5 and T6. The emitter of transistor T6 is connected to the collector of transistor T3. The output currents Io1 and Io2 of the circuit correspond to the collector currents of the cascode transistors T5 and T6 while the input current Iin originates from the collector of the first cascode transistor T4. The operation of this circuit is similar to the one of FIG. 1.
For a given input current Iin, the collector current Ic4 of transistor T4 is equal to Iin less the three base currents of transistors T4, T5, T6. Supposing that the cascode transistors T4, T5, T6 have the same emitter surface area, those base currents are identical. So, Ic4=Iin-3Ib. The emitter current Ie4 of transistor T4 is Ie4=Iin-2Ib. The current Ie4 is also equal to the sum of the collector current Ic1 of transistor T1 and of the three base currents of transistors T1, T2, T3.
Assuming that the emitter surface areas of the mirror transistors T1, T2, T3 are equal to the emitter surface areas of the cascode transistors T4, T5, T6, each base current is equal to Ib. So, Ie1=Ie4-3Ib=Iin-5Ib. The emitter current Ie1 of transistor T1 is Ie1=Iin-4Ib. As transistors T1, T2, T3 have the same emitter-base voltage Vbe, they have the same emitter current. Therefore, the emitter currents Ie2 and Ie3 of transistors T2 and T3 are Ie2=Ie3=Ie1=Iin-4Ib. Their collector current Ic corresponds to the emitter current Ie less one base current Ib and is equal to Iin-5Ib. Those collector currents Ic2 and Ic3 are respectively identical to the emitter currents Ie5 and Ie6 of transistors T5 and T6. The output currents Io1 and Io2 that correspond to the collector currents of transistors T5 and T6 are therefore: Io1=Io2-Iin-6Ib.
The limitation of the Early effect is due to the fact that the collector-emitter voltages of the mirror transistors T1, T2, T3 are fixed at an identical value equal to Vbe. Therefore, the use of cascode transistors makes the outputs Io1 and Io2 less sensitive to variations of the supply voltage Vcc and of the loads, the outputs having an high impedance. However, as indicated above, in this circuit, the mirror ratio is 1-6/.beta., that is the "error" is twice higher than in the example of FIG. 1. The drawbacks indicated in connection with FIG. 1 in this respect are therefore increasing.
FIG. 3 shows a Wilson-type current mirror. This circuit corresponds to the one of FIG. 2, but the connecting node A of the bases of transistors T1, T2 and T3 corresponds now to the collector of transistor T2 and not of transistor T1. Therefore, the effect of the base current Ib is compensated on the first output Io1 but the mirror ratio remains poor for the other outputs.
For a given input current Iin, the collector current Ic4 of transistor T4 is equal, as before, to this current Iin less the three base currents of transistors T4, T5, T6. Those base currents being identical, Ic4=Iin-3Ib, Ie4=Ic4+Ib=Iin-2Ib, and Ie1=Iin-Ib. As the transistors T1, T2 and T3 have the same base-emitter voltage Vbe, they have identical emitter currents equal to Iin-Ib. Their collector current Ic corresponds to their emitter current Ie less their base current Ib and is equal to Iin-2Ib. The emitter current Ie5 of transistor T5 is equal to this collector current plus the three base currents of transistors T1, T2 and T3, that is: Iin+Ib. Therefore, the collector current of transistor T5 which corresponds to the first output current Io1 is equal to Iin. However, the collector current of transistor T6 that corresponds to the current of the second output Io2 is equal to Iin-3Ib.
Accordingly, this circuit provides a good mirror ratio on the first output but a poor mirror ratio on the second one. The matching ratio is equal to 1-3/.beta., which is unsatisfactory.
FIG. 4 shows another circuit for reducing the effect of the gain .beta. of the transistors on the mirror ratio while keeping a matching ratio equal to 1. This circuit is similar to the one of FIG. 3 but the connection node A of the bases of transistors T1, T2 and T3 now corresponds to the emitter of a multi-collector transistor T7. Transistor T7 aims at compensating the collector currents of mirror transistors T1, T2 and T3. The base of transistor T7 is connected to the connection node B of the bases of the cascode transistors T4, T5 and T6. The two collectors of transistor T7 are respectively connected to the collector of transistor T5 and the collector of transistor T6.
As before, for a given input current Iin, one obtains Ie1=Ie2=Ie3=In-Ib. The collector currents Ic5 and Ic6 of the cascode transistors T5 and T6 are Ic5=Ic6=Iin-3Ib (The effect of the base current Ib7 of transistor T7 on the value of the collector current Ic1 of transistor T1 is neglected; this is due to the fact that this base current is of the second order with respect to Ib, transistor T7 being fed by the three base currents of the mirror transistors T1, T2 and T3). The collectors of transistor T7 have the same surface. Therefore, the emitter current Ie7 is divided between the collectors. As Ie7=3Ib and as the base current of transistor T7 is neglected, the current on each collector is 1.5Ib. Therefore, the value of the output currents Io1 and Io2 is Io1=Io2=Iin-1.5Ib.
So, the circuit of FIG. 4 improves the mirror ratio with respect to the former circuits while the matching ratio remains equal to 1. Another circuit for obtaining a multiple output mirror current wherein the mirror ratio is substantially equal to 1 for all the outputs is shown in FIG. 5.
It comprises three mirror transistors T1, T2 and T3 and three cascode transistors T4, T5 and T6. It also comprises two transistor pairs T7, T8 and T9, T10 respectively associated with current generators 1 and 2. The transistors T7 and T9 are NPN transistors and their collectors are connected to the supply voltage Vcc. Their emitters are connected to a first terminal of a current source, respectively 1 and 2, whose other terminal is grounded. The emitters are also connected to the respective base of the PNP transistors T8 and T10. The collectors of transistors T8 and T10 are grounded. Their respective emitters are connected to the respective base nodes B and A of the cascode transistors T4, T5, T6 and of the mirror transistors T1, T2, T3. The base of transistor T7 is connected to the collector of transistor T4 and the base of transistor T9 is connected to the collector of transistor T2.
With an input Iin, the collector current Ic4 of transistor T4 is equal to Iin, neglecting the base current Ib7 of transistor T7. So, Ie1=Iin+Ib and Ie1=Ie2=Ie3=Iin+2Ib. Therefore, the collector currents of transistors T5 and T6, that is the output currents Io1 and Io2, are equal to Iin.
This result is obtained while neglecting the effect of the base currents Ib7 and Ib9 on the collector currents Ic4 and Ic2 of transistors T4 and T2. Accordingly, such a circuit has suitable characteristics when the current Iin is high. However, it has a poor accuracy on a large range of input currents. This is due to the fact that, when the input current is low, the base currents Ib7 and Ib9 can no longer be neglected. In this case, those base currents are not, like for transistor T7 of FIG. 4, second order base currents, but are currents provided by current sources. Such a drawback is particularly significative when Iin is subject to high variations; for an AC current, a deformation of the output currents is caused.
An object of the invention is to provide a multiple output current mirror that has a good mirror ratio, equal to unity and that is stable when the input current varies.
Another object of the invention is to provide such a mirror ratio that is identical for a multiple output current mirror, even if the number of outputs is increased.